Overall chip performance may be severely limited by interconnect performance for chips at scaled nodes, e.g., the 7 nm node and beyond. As feature sizes are scaled, metal pitches and transistors are also scaled. The reduction in metal pitch (i.e., reducing the distance between the metal lines), can result in an increase in capacitance per unit length. Furthermore, a reduction in the cross-sectional area of the interconnect, associated also with a reduction in metal pitches, can result in a non-linear increase in the resistivity of the interconnect, thus increasing (e.g., degrading) the interconnect via and line resistances and further worsening (e.g., degrading) overall chip performance.
To compensate for high via and line resistances, repeaters may be inserted to boost the signal level for long routing wires, e.g., wires higher than in metal2 layer. At the 7 nm and beyond, repeaters may be inserted much more frequently due to the non-linear increase in line resistances. However, repeaters may also be degraded due to high via resistances that are used to connect repeaters to higher metal routing layers. Furthermore, due to the increase in number of repeaters and width of the repeaters required, they may consume a significant area of the chip at a scaled node.
The above information disclosed in this Background section is provided for enhancement of understanding of the background of the invention, and therefore, it may contain information that does not constitute prior art.